1. Field of the Invention
This invention relates to an improved memory cell and to a two-rail data bus line configuration by which to either read and write cell data or power the memory cell.
2. Prior Art
Conventional memory cells typically require relatively numerous bus lines as well as several large sized components in order to either access the cell for reading or writing binary information and for providing power to the cell. As a result thereof, the overall size and cost of the conventional memory cell is undesirably increased. Thus, the area consumed by an array comprised of conventional memory cells is also correspondingly increased.
What is more, in order to power an array comprised of conventional memory cells so as to refresh the logical state of each of the cell data nodes, all of the memory cells of the array are scanned individually. Therefore, the speed of operating the array is undesirably slowed. Moreover, relatively complex multiplexing means are required to both power and scan the conventional memory cells comprising the array.